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DR200.AS
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1990-11-14
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10KB
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369 lines
;/*
; * Copyright 1988 by the Radio Amateur Telecommunications Society
; * and Thomas A. Moulton, W2VY
; *
; * This software may only be modified, copied, distributed or
; * executed for non-profit purposes by individuals operating
; * systems in the Amateur Radio Service. Credit to the
; * author(s) and to the Radio Amateur Telecommunications Society
; * must be made in modules where RATS provided software is used,
; * and in any announcements and documentation.
; *
; * As a non-profit, research and development organization, the
; * Radio Amateur Telecommunications Society distributes software
; * in both executable and source forms. This policy is in place
; * to encourage the development and distribution of OSI-based,
; * networking tools. In order to protect the interests of the
; * Society and the authors, we have placed some conditions
; * of use on the software. Other groups are encouraged
; * to place the same or similar guidelines on
; * software they produce.
; *
; * The Radio Amateur Telecommunications Society reserves the right
; * to specify and alter the terms under which software provided by
; * the Society may be used. This policy is consistent with the
; * objective of uniform and consistent "Open Systems Interconnections."
; *
; * All acceptable Amateur Radio related uses of this software
; * will be outlined in the "ROSE Implementer's Guide". Individuals
; * or organizations wishing to add to, or modify the provisions of
; * the guide to accommodate local or evolutionary requirements
; * should document the proposed change(s) and forward them to the
; * Society. If accepted, written notification will be provided by
; * the Society to the submitting organization or individual(s).
; * The Society will then issue a "ROSE Implementer's Guide Change
; * Notice". Periodically, the Society will re-issue the "ROSE
; * Implementer's Guide" and incorporate the text of the change
; * notices. This procedure has been put in to place to ensure
; * compatibility between systems and to ensure their "Openness"
; * and interoperability.
; *
; * No part of this software may be used in other packages
; * without prior authorization from the author or the Society.
; * Software incorporating this module, all or in part, must be
; * provided to the Society prior to distribution or use by
; * anyone not directly involved in testing of the revised
; * environment. Current releases of the combined software must
; * be provided to the Society in both source and executable
; * forms. Adequate documention to produce an executable module
; * from the provided source must also be included.
; *
; * Non-Amateur Radio non-profit uses may be authorized on a case
; * by case basis. Inquiries for such use may be made in writing
; * to the Society. Non-commercial uses consistent with the
; * general principles of Open Systems Interconnection Reference
; * Model will be generally considered with favor.
; *
; * Commercial licensing of the software is also available based
; * on normal commercial terms. Licensing inquiries should be
; * directed to the Society. Commercial licensing of the standard
; * software will be done in situations which materially benefit
; * the Amateur Radio Packet Network. Additional licensing is
; * reserved by the individual authors.
; *
; * The Radio Amateur Telecommunications Society provides this software
; * on an "as is" basis. The Society assumes no liability for
; * loss incurred through the use of this software. Amateur Radio
; * use of this software implies non-commercial and voluntary
; * development, deployment and use of this software in a "Amateur",
; * non-commercial service. Commercial users are encouraged to
; * inspect their copies of the source code. Source code modification
; * licenses are available if a combined Object and Source Code
; * license was not originally established.
; *
; * The Society may be contacted by writing or calling at:
; *
; * The Radio Amateur Telecommunications Society
; * 206 North Vivyen Street.
; * Bergenfield, New Jersey 07621
; *
; * Telephone: 201-387-8896
; *
; */
;
; System Init for ROM
;
psect text,pure
*INCLUDE RCONFIG.LIB
*INCLUDE STRUCT.LIB
MCTS EQU 20H
MDCD EQU 08H
MRTS EQU 02H
POWER_FAIL EQU 0150H
GLOBAL CLKBIT, TICKCNT, HDLI
psect text
start: di ;Insure NO int's!!
jp POWER_FAIL ;Power Failure, check memory, etc
jp INIT_HDW ;Set up SDS's based on the machine type
jp INIT_LED ;Init Led's
jp UPD_LED ;Change Led's (toggle)
HALT ;Nothing to do when "halted"
RET
NOP
global amul, brelop, wrelop, csv, cret
RST2: jp (hl) ;for optimizer **********'0010'**************
defm 'PacComm'
RST3: jp amul ;for optimizer **********'0018'**************
defm 'DR200'
RST4: jp brelop ;for optimizer **********'0020'**************
defb NUMCH+30h
defm 'PORT'
RST5: jp wrelop ;for optimizer **********'0028'**************
defm 'W2VY'
defb 0
RST6: jp csv ;for optimizer **********'0030'**************
defm 'ROSE'
defb 0
RST7: ex (sp),hl ;for optimizer **********'0038'**************
pop hl
jp cret
tickcnt: defb 6 ;Clock is at 300 hz
defw 0 ;Pointer to Terminal baud rate
defw 0 ;Pointer to Radio baud rate byte (SCCBI)
ileds: defb 0 ;Initial LED Pattern
defw SDSI0, SDSI1
global SDS0, SDS1
; Initialize the SIO data structures
INIT_HDW:
LD HL,SDSI0 ;Copy from ROM
LD DE,SDS0 ;To RAM
LD BC,SDSILEN
LDIR
LD HL,SDSI1 ;Copy from ROM
LD DE,SDS1 ;To RAM
LD BC,SDSILEN
LDIR
COND NUMCH .gt. 2
GLOBAL SDS2
LD HL,SDSI2 ;Copy from ROM
LD DE,SDS2 ;To RAM
LD BC,SDSILEN
LDIR
ENDC
COND NUMCH .gt. 3
GLOBAL SDS3
LD HL,SDSI3 ;Copy from ROM
LD DE,SDS3 ;To RAM
LD BC,SDSILEN
LDIR
ENDC
LD A,MCTS ;DR200 Clock bit (CTS)
LD (CLKBIT),A ;Save it
LD A,(tickcnt)
LD (TICKCNT),A ;Number of Interrupts/Tick to 10ms
LD A,09
LD C,8
OUT (C),A
LD A,0C0H ;Master Reset for SCC
OUT (C),A
NOP
NOP ;Wait for it to happen
COND NUMCH .gt. 2
LD A,09
LD C,0ch ;Daughter Board
OUT (C),A
LD A,0C0H ;Master Reset for SCC
OUT (C),A
ENDC
; Both Radio Port PTT/DCD is always normal
LD HL,0FF02h ;PTTMSK1=MRTS, PTTMSK2=FF
XOR A
LD B,A ;DCD is Normal - No Toggle
LD (SDS0+PTTMSK1),HL
LD (SDS0+DCDTGL),A
LD (SDS1+PTTMSK1),HL
LD (SDS1+DCDTGL),A
LD IY,SDS0
CALL HDLI
LD IY,SDS1
CALL HDLI
COND NUMCH .gt. 2
LD IY,SDS2
CALL HDLI
ENDC
COND NUMCH .gt. 3
LD IY,SDS3
CALL HDLI
ENDC
RET
INIT_LED: ;Enter with (_COLD) in A and B
LD D,5
LD IY,SDS0 ;Get address of port 0
LD C,(IY+CPORT) ; CON Led
OUT (C),D ;WR 5
AND 80h ; CON Led is High Bit
LD E,A
LD A,(IY+WR5REG) ;Get Current value
AND 7Fh ;Ignore DTR
OR E ;Set DTR
OUT (C),A
LD IY,SDS1 ;Get to SDS1
LD C,(IY+CPORT) ; STA Led
OUT (C),D ;WR 5
LD A,B
AND 40h ;STA Led is second bit
SLA A
LD E,A
LD A,(IY+WR5REG)
AND 7Fh ;Ignore DTR
OR E ;Set DTR
OUT (C),A ;LEDS Now indicate Restart Cause
RET
UPD_LED:
call csv
ld hl,SDS0 ;Get to SDS0
call toggle
ld hl,SDS1 ;Get to SDS1
call toggle
jp cret
toggle:
ld de,CPORT
add hl,de
ld c,(hl) ;Get command port address
ld de,WR5REG-CPORT
add hl,de
ld b,5 ;WR 5
DI
ld a,(hl)
xor 80h
ld (hl),a
out (c),b
out (c),a
EI
ret
GLOBAL SDSI0, SDSI1
SDSI0: DEFB 0 ;Channel number
DEFB 11 ;SCC data port
DEFB 9 ;SCC control port
DEFW DWAIT0
DEFW TXDELAY0
DEFW SCCBI ;SYNC CONFIG
DEFB SCCAIL ;LEN
DEFB 0 ;Flags
DEFB 0E9h ;WR5REG (DTR Now On, CON)
SDSI1: DEFB 1 ;Channel number
DEFB 10 ;SIO data port
DEFB 8 ;SIO control port
DEFW DWAIT1
DEFW TXDELAY1
DEFW SCCBI ;8530 Config
DEFB SCCBIL ;LEN
DEFB MTIMER ;Line for timer
DEFB 069h ;WR5REG (DTR is Now Off, STA) RTS Off
ENDC
COND NUMCH .gt. 2
GLOBAL SDSI2
SDSI2: DEFB 2 ;Channel number
DEFB 0Fh ;SIO data port
DEFB 0Eh ;SIO control port
DEFW DWAIT2
DEFW TXDELAY2
DEFW SCCCI ;SYNC CONFIG
DEFB SCCCIL ;LEN
DEFB 0 ;Flags
DEFB 0 ;WR5REG
ENDC
COND NUMCH .gt. 3
GLOBAL SDSI3
SDSI3: DEFB 3 ;Channel number
DEFB 0Dh ;SIO data port
DEFB 0Ch ;SIO control port
DEFW DWAIT3
DEFW TXDELAY3
DEFW SCCDI ;SYNC CONFIG
DEFB SCCDIL ;LEN
DEFB 0 ;Flags
DEFB 0 ;WR5REG
ENDC
; Fixed data
; SCC SYNC initialization block.
SCCBI: DEFB 4,0A0H ;X32, SDLC, Sync
DEFB 10,0A0H ;Init CRC, NRZI
DEFB 7,7EH ;Sync Definitition (No S!!t)
DEFB 2,0H ;Interrupt Vector
DEFB 3,0DAH ;8 bit Rx, Enter Hunt, RXCRC, Sync Load Inh.
DEFB 5,68H ;8 Bit Tx, Tx Enable
DEFB 11,68H ;RXC = DPLL Out, TXC = TRxC, TRxC=IN,
DEFB 14,0A0H ;DPLL Source = RTxC (x32 clock)
DEFB 5,69H ;8 bit Tx, Tx Enable, TX CRC Enable
DEFB 3,0DBH ;Same as 3 above, RX Enable
DEFB 14,20H ;Enter Search Mode
DEFB 15,0E8H ;Enable Interrupts on
DEFB 10H,10H ;Reset External Interupts, Twice
DEFB 1,13H ;Interrupt on Receive and Xmit
SCCAIL EQU $-SCCBI
DEFB 9,9 ;Master Interrupt Enable, Vector Includes Stat
SCCBIL EQU $-SCCBI
COND NUMCH .gt. 2
;DR200A 8530 VALUES FOR INITIALIZAITON
; SCC ASYNC initialization block.
SCCCI: DEFB 2,10h ;Set Up Interrupt Vector
DEFB 14h ;WR 4 + Reset Ext Intr
DEFB 84H ;32xClk + 1Stop + NoParity
DEFB 11,00H ;TXC, RXC - RTxC Pin
DEFB 3 ;WR 3
DEFB 0C1H ;8bit + RxEnable
DEFB 5 ;WR 5
DEFB 0E8H ;DTR On + 8bit + TxEnable + RTS Off
DEFB 11h ;WR 1 + Reset Ext intr
DEFB 00011111B ;Enable rx, ext ints
SCCCIL EQU $-SCCCI
; SCC SYNC initialization block.
SCCDI: DEFB 4,00H ;X1, SDLC, Sync
DEFB 10,80H ;Init CRC, NRZ
DEFB 7,7EH ;Sync Definitition (No S!!t)
DEFB 2,10H ;Interrupt Vector
DEFB 3,0DAH ;8 bit Rx, Enter Hunt, RXCRC, Sync Load Inh.
DEFB 5,68H ;8 Bit Tx, Tx Enable
DEFB 11,08H ;RXC = RTxC (x1), TXC = TRxC, TRxC=IN,
DEFB 14,60H ;Disable DPLL
DEFB 5,69H ;8 bit Tx, Tx Enable, TX CRC Enable
DEFB 3,0DBH ;Same as 3 above, RX Enable
DEFB 14,20H ;Enter Search Mode
DEFB 15,0E8H ;Enable Interrupts on
DEFB 10H,10H ;Reset External Interupts, Twice
DEFB 1,13H ;Interrupt on Receive and Xmit
DEFB 9,9 ;Master Interrupt Enable, Vector Includes Stat
SCCDIL EQU $-SCCBI
ENDC